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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. mos integrated circuit pd431000a 1m-bit cmos static ram 128k-word by 8-bit data sheet document no. m11657ejdv0ds00 (13th edition) date published november 2008 printed in japan 1990, 1993, 1995 description the pd431000a is a high speed, low power, and 1,048,576 bits (131,072 words by 8 bits) cmos static ram. the pd431000a has two chip enable pins (/ce1, ce2) to extend the capacity. and battery backup is available. in addition to this, a and b versions are low voltage operations. the pd431000a is packed in 32-pin plastic dip, 32- pin plastic sop and 32-pin plastic tsop (i) (8 13.4 mm) and (8 20 mm). features ? 131,072 words by 8 bits organization ? fast access time: 70, 85, 100, 120, 150 ns (max.) ? low voltage operation (a version: v cc = 3.0 to 5.5 v, b version: v cc = 2.7 to 5.5 v) ? operating ambient temperature: t a = 0 to 70 c ? low v cc data retention: 2.0 v (min.) ? output enable input for easy application ? two chip enable inputs: /ce1, ce2 part number access time operating s upply operating ambient supply current ns (max.) voltage temperature at operating at standby at data retention v c ma (max.) a (max.) a (max.) note1 pd431000a-xxl 70, 85 4.5 to 5.5 0 to 70 70 100 15 pd431000a-xxll 20 3 pd431000a-axx 70 note2 , 100 3.0 to 5.5 35 note3 13 note5 pd431000a-bxx 70 note2 , 100, 120, 150 2.7 to 5.5 30 note4 11 note6 notes 1. t a 40 c 2. v cc = 4.5 to 5.5 v 3. 70 ma (v cc > 3.6 v) 4. 70 ma (v cc > 3.3 v) 5. 20 a (v cc > 3.6 v) 6. 20 a (v cc > 3.3 v)
data sheet m11657ejdv0ds 2 pd431000a ordering information (1/2) part number package access time operat ing supply operating ambient remark ns (max.) voltage temperature v c pd431000acz-70l 32-pin plastic dip 70 4.5 to 5.5 0 to 70 l version pd431000acz-85l (15.24mm (600)) 85 pd431000acz-70ll 70 ll version pd431000acz-85ll 85 pd431000agw-70l 32-pin plastic sop 70 4.5 to 5.5 l version pd431000agw-85l (13.34 mm (525)) 85 pd431000agw-70ll 70 ll version pd431000agw-85ll 85 pd431000agw-a10 100 3.0 to 5.5 a version pd431000agw-b12 120 2.7 to 5.5 b version pd431000agw-b15 150 pd431000agz-70ll-kjh 32-pin plastic tsop(i) 70 4.5 to 5.5 ll version pd431000agz-b15-kjh (8x20) (normal bent) 150 2.7 to 5.5 b version pd431000agz-70ll-kkh 32-pin plastic tsop(i) 70 4.5 to 5.5 ll version (8x20) (reverse bent) pd431000agu-b10-9jh 32-pin plastic tsop (i) 100 2.7 to 5.5 b version pd431000agu-b12-9jh (8x13.4) (normal bent) 120 pd431000agu-b15-9jh 150 pd431000agu-b10-9kh 32-pin plastic tsop(i) 100 (8x13.4) (reverse bent)
data sheet m11657ejdv0ds 3 (2/2) part number package access time operat ing supply operating ambient remark ns (max.) voltage temperature v c pd431000agw-70l-a 32-pin plastic sop 70 4.5 to 5.5 0 to 70 l version pd431000agw-85l-a (13.34 mm (525)) 85 pd431000agw-70ll-a 70 ll version pd431000agw-85ll-a 85 pd431000agw-a10-a 100 3.0 to 5.5 a version pd431000agw-b12-a 120 2.7 to 5.5 b version pd431000agw-b15-a 150 pd431000agz-70ll-kjh-a 32-pin plastic tsop(i) 70 4.5 to 5.5 ll version pd431000agz-b10-kjh-a (8x20) (normal bent) 100 2.7 to 5.5 b version pd431000agz-70ll-kkh-a 32-pin plastic tsop(i) 70 4.5 to 5.5 ll version (8x20) (reverse bent) pd431000agu-b10-9jh-a 32-pin plastic tsop (i) 100 2.7 to 5.5 b version pd431000agu-b12-9jh-a (8x13.4) (normal bent) 120 pd431000agu-b15-9jh-a 150 pd431000agu-b10-9kh-a 32-pin plastic tsop(i) 100 (8x13.4) (reverse bent) remark products with -a at the end of the part number are lead-free products.
data sheet m11657ejdv0ds 4 pd431000a pin configurations (marking side) /xxx indicates active low signal. 32-pin plastic dip (15.24 mm (600)) [ pd431000acz-xxl] [ pd431000acz-xxll] nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 gnd v cc a15 ce2 /we a13 a8 a9 a11 /oe a10 /ce1 i/o8 i/o7 i/o6 i/o5 i/o4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a0 - a16 : address inputs i/o1 - i/o8 : data inputs / outputs /ce1, ce2 : chip enable 1, 2 /we : write enable /oe : output enable v cc : power supply gnd : ground nc : no connection remark refer to package drawings for the 1-pin index mark.
data sheet m11657ejdv0ds 5 pd431000agw-xxl] [ pd431000agw-xxll] [ pd431000agw-axx] [ pd431000agw-bxx] [ pd431000agw-xxl-a] [ pd431000agw-xxll-a] [ pd431000agw-axx-a] [ pd431000agw-bxx-a] nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 gnd v cc a15 ce2 /we a13 a8 a9 a11 /oe a10 /ce1 i/o8 i/o7 i/o6 i/o5 i/o4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a0 - a16 : address inputs i/o1 - i/o8 : data inputs / outputs /ce1, ce2 : chip enable 1, 2 /we : write enable /oe : output enable v cc : power supply gnd : ground nc : no connection remark refer to package drawings for the 1-pin index mark.
data sheet m11657ejdv0ds 6 pd431000a 32-pin plastic tsop(i) (8x20) (normal bent) [ pd431000agz-xxll-kjh] [ pd431000agz-bxx-kjh] [ pd431000agz-xxll-kjh-a] [ pd431000agz-bxx-kjh-a] a11 a9 a8 a13 /we ce2 a15 v cc nc a16 a14 a12 a7 a6 a5 a4 /oe a10 /ce1 i/o8 i/o7 i/o6 i/o5 i/o4 gnd i/o3 i/o2 i/o1 a0 a1 a2 a3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32-pin plastic tsop(i) (8x20) (reverse bent) [ pd431000agz-xxll-kkh] [ pd431000agz-xxll-kkh-a] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 /oe a10 /ce1 i/o8 i/o7 i/o6 i/o5 i/o4 gnd i/o3 i/o2 i/o1 a0 a1 a2 a3 a11 a9 a8 a13 /we ce2 a15 v cc nc a16 a14 a12 a7 a6 a5 a4 a0 - a16 : address inputs /oe : output enable i/o1 - i/o8 : data inputs / outputs v cc : power supply /ce1, ce2 : chip enable 1, 2 gnd : ground /we : write enable nc : no connection remark refer to package drawings for the 1-pin index mark.
data sheet m11657ejdv0ds 7 32-pin plastic tsop(i) (8x13.4) (normal bent) [ pd431000agu-bxx-9jh] [ pd431000agu-bxx-9jh-a] a11 a9 a8 a13 /we ce2 a15 v cc nc a16 a14 a12 a7 a6 a5 a4 /oe a10 /ce1 i/o8 i/o7 i/o6 i/o5 i/o4 gnd i/o3 i/o2 i/o1 a0 a1 a2 a3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32-pin plastic tsop(i) (8x13.4) (reverse bent) [ pd431000agu-bxx-9kh] [ pd431000agu-bxx-9kh-a] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 /oe a10 /ce1 i/o8 i/o7 i/o6 i/o5 i/o4 gnd i/o3 i/o2 i/o1 a0 a1 a2 a3 a11 a9 a8 a13 /we ce2 a15 v cc nc a16 a14 a12 a7 a6 a5 a4 a0 - a16 : address inputs i/o1 - i/o8 : data inputs / outputs /ce1, ce2 : chip enable 1, 2 /we : write enable /oe : output enable v cc : power supply gnd : ground nc : no connection remark refer to package drawings for the 1-pin index mark.
data sheet m11657ejdv0ds 8 pd431000a block diagram address buffer address buffer row decoder memory cell array 1,048,576 bits input data controller a0 a16 sense amplifier / switching circuit column decoder /ce1 /we /oe ce2 output data controller v cc gnd i/o1 i/o8 truth table /ce1 ce2 /oe /we mode i/o supply current h not selected high impedance i sb l l h h h output disable i cca l h l h read d out l h l write d in remark : v ih or v il
data sheet m11657ejdv0ds 9 absolute maximum ratings parameter symbol condition rating unit supply voltage v cc ?0.5 note to +7.0 v input / output voltage v t ?0.5 note to v cc + 0.5 v operating ambient temperature t a 0 to 70 c storage temperature t stg ?55 to +125 c note ?3.0 v (min.) (pulse width: 30 ns) caution exposing the device to stress above those listed in absolute maximum rating could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this speci fication. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition pd431000a-xxl pd431000a-axx pd431000a-bxx unit pd431000a-xxll min. max. min. max. min. max. supply voltage v cc 4.5 5.5 3.0 5.5 2.7 5.5 v high level input voltage v ih 2.2 v cc +0.5 2.2 v cc +0.5 2.2 v cc +0.5 v low level input voltage v il ?0.3 note +0.8 ?0.3 note +0.5 ?0.3 note +0.5 v operating ambient temperature t a 0 70 0 70 0 70 c note ?3.0 v (min.) (pulse width: 30 ns) capacitance (t a = 25 c, f = 1 mhz) parameter symbol test conditions min. typ. max. unit input capacitance c in v in = 0 v 6 pf input / output capacitance c i/o v i/o = 0 v 10 pf remarks 1. v in : input voltage v i/o : input / output voltage 2. these parameters ar e not 100% tested.
data sheet m11657ejdv0ds 10 pd431000a dc characteristics (recommended operating c onditions unless otherwise noted) (1/2) parameter symbol test condition pd431000a-xxl pd431000a-xxll pd431000a-axx unit min. typ. max. min. typ. max. min. typ. max. input leakage i li v in = 0 v to v cc ?1.0 +1.0 ?1.0 +1.0 ?1.0 +1.0 a current i/o leakage i lo v i/o = 0 v to v cc , ?1.0 +1.0 ?1.0 +1.0 ?1.0 +1.0 a current /ce1 = v ih or ce2 = v il or /we = v il or /oe = v ih operating i cca1 /ce1 = v il , ce2 = v ih , 40 70 40 70 40 70 ma supply current i i/o = 0 ma minimum cycle time v cc 3.6 v ? ? 35 i cca2 /ce1 = v il , ce2 = v ih , i i/o = 0 ma, 15 15 15 cycle time = v cc 3.6 v ? ? 8 i cca3 /ce1 0.2 v, ce2 v cc ? 0.2 v, 10 10 10 cycle time = 1 s, i i/o = 0 ma, v il 0.2 v, v ih v cc ? 0.2 v v cc 3.6 v ? ? 8 standby i sb /ce1 = v ih or ce2 = v il 3 3 3 ma supply current v cc 3.6 v ? ? 2 i sb1 /ce1 v cc ? 0.2 v, 2 100 1 20 1 20 a ce2 v cc ? 0.2 v v cc 3.6 v ? ? 0.5 13 i sb2 ce2 0.2 v 2 100 1 20 1 20 v cc 3.6 v ? ? ? ? 0.5 13 high level v oh1 i oh = ?1.0 ma, v cc 4.5 v 2.4 2.4 2.4 v output voltage i oh = ?0.5 ma ? ? 2.4 v oh2 i oh = ?0.02 ma ? ? v cc ?0.1 low level v ol1 i ol = 2.1 ma, v cc 4.5 v 0.4 0.4 0.4 v output voltage i ol = 1.0 ma ? ? 0.4 v ol2 i ol = 0.02 ma ? ? 0.1 remarks 1. v in : input voltage v i/o : input / output voltage 2. these dc characteristics are in comm on regardless product classification.
data sheet m11657ejdv0ds 11 parameter symbol test condition pd431000a-bxx unit min. typ. max. input leakage current i li v in = 0 v to v cc ?1.0 +1.0 a i/o leakage current i lo v i/o = 0 v to v cc , /ce1 = v ih or ce2 = v il ?1.0 +1.0 a or /we = v il or /oe = v ih operating supply current i cca1 /ce1 = v il , ce2 = v ih , i i/o = 0 ma 40 70 ma minimum cycle time v cc 3.3 v 30 i cca2 /ce1 = v il , ce2 = v ih , i i/o = 0 ma, 15 cycle time = v cc 3.3 v 7 i cca3 /ce1 0.2 v, ce2 v cc ? 0.2 v, 10 cycle time = 1 s, i i/o = 0 ma, v il 0.2 v, v ih v cc ? 0.2 v v cc 3.3 v 7 standby supply current i sb /ce1 = v ih or ce2 = v il 3 ma v cc 3.3 v 2 i sb1 /ce1 v cc ? 0.2 v, ce2 v cc ? 0.2 v 1 20 a v cc 3.3 v 0.5 11 i sb2 ce2 0.2 v 1 20 v cc 3.3 v 0.5 11 high level output voltage v oh1 i oh = ?1.0 ma, v cc 4.5 v 2.4 v i oh = ?0.5 ma 2.4 v oh2 i oh = ?0.02 ma v cc ?0.1 low level output voltage v ol1 i ol = 2.1 ma, v cc 4.5 v 0.4 v i ol = 1.0 ma 0.4 v ol2 i ol = 0.02 ma 0.1 remarks 1. v in : input voltage v i/o : input / output voltage 2. these dc characteristics are in comm on regardless product classification.
data sheet m11657ejdv0ds 12 pd431000a ac characteristics (recommended operati ng conditions unless otherwise noted) ac test conditions [ pd431000a-70l, pd431000a-85l, pd431000a-70ll, pd431000a-85ll] input waveform (rise and fall time 5 ns) test points 1.5 v 1.5 v 2.2 v 0.8 v output waveform test points 1.5 v 1.5 v output load ac characteristics should be measur ed with the following output load conditions. figure 1 figure 2 (t aa , t co1 , t co2 , t oe , t oh ) (t lz1 , t lz2 , t olz , t hz1 , t hz2 , t ohz , t whz , t ow ) +5 v i/o (output) 1.8 k 5 pf c l 990 +5 v i/o (output) 1.8 k 100 pf c l 990 remark c l includes capacitance of the pr obe and jig, and stray capacitance. [ pd431000a-a10, pd431000a-b10, pd431000a-b12, pd431000a-b15] input waveform (rise and fall time 5 ns) test points 1.5 v 1.5 v 2.2 v 0.5 v output waveform test points 1.5 v 1.5 v output load ac characteristics should be measur ed with the following output load conditions. part number output load condition t aa , t co1 , t co2 , t oe , t oh t lz1 , t lz2 , t olz , t hz1 , t hz2 , t ohz , t whz , t ow pd431000a-a10, pd431000a-b10, pd431000a-b12 1ttl + 50 pf 1ttl + 5 pf pd431000a-b15 1ttl + 100 pf 1ttl + 5 pf
data sheet m11657ejdv0ds 13 parameter symbol v cc 4.5 v v cc 3.0 v unit condition pd431000a-70 pd431000a-85 pd431000a-a10 pd431000a-axx pd431000a-bxx min. max. min. max. min. max. read cycle time t rc 70 85 100 ns address access time t aa 70 85 100 ns note /ce1 access time t co1 70 85 100 ns ce2 access time t co2 70 85 100 ns /oe to output valid t oe 35 45 50 ns output hold from address change t oh 10 10 10 ns /ce1 to output in low impedance t lz1 10 10 10 ns ce2 to output in low impedance t lz2 10 10 10 ns /oe to output in low impedance t olz 5 5 5 ns /ce1 to output in high impedance t hz1 25 30 35 ns ce2 to output in high impedance t hz2 25 30 35 ns /oe to output in high impedance t ohz 25 30 35 ns note see the output load . remark these ac characteristics are in common regardless of package types. read cycle (2/2) parameter symbol v cc 2.7 v unit condition pd431000a-b10 pd431000a-b12 pd431000a-b15 min. max. min. max. min. max. read cycle time t rc 100 120 150 ns address access time t aa 100 120 150 ns note /ce1 access time t co1 100 120 150 ns ce2 access time t co2 100 120 150 ns /oe to output valid t oe 50 60 70 ns output hold from address change t oh 10 10 10 ns /ce1 to output in low impedance t lz1 10 10 10 ns ce2 to output in low impedance t lz2 10 10 10 ns /oe to output in low impedance t olz 5 5 5 ns /ce1 to output in high impedance t hz1 35 40 50 ns ce2 to output in high impedance t hz2 35 40 50 ns /oe to output in high impedance t ohz 35 40 50 ns note see the output load . remark these ac characteristics are in common regardless of package types.
data sheet m11657ejdv0ds 14 pd431000a read cycle timing chart t hz2 t rc t oh t hz1 t lz2 t co2 t lz1 t co1 t aa high impedance data out ce2 (input) /ce1 (input) address (input) i/o (output) t olz t oe t ohz /oe (input) remark in read cycle, /we should be fixed to high level.
data sheet m11657ejdv0ds 15 parameter symbol v cc 4.5 v v cc 3.0 v unit condition ` pd431000a-70 pd431000a-85 pd431000a-a10 pd431000a-axx pd431000a-bxx min. max. min. max. min. max. write cycle time t wc 70 85 100 ns /ce1 to end of write t cw1 55 70 80 ns ce2 to end of write t cw2 55 70 80 ns address valid to end of write t aw 55 70 80 ns address setup time t as 0 0 0 ns write pulse width t wp 50 60 60 ns write recovery time t wr 5 5 0 ns data valid to end of write t dw 35 35 60 ns data hold time t dh 0 0 0 ns /we to output in high impedance t whz 25 30 35 ns note output active from end of write t ow 5 5 5 ns note see the output load . remark these ac characteristics are in common regardless package types. write cycle (2/2) parameter symbol v cc 2.7 v unit condition pd431000a-b10 pd431000a-b12 pd431000a-b15 min. max. min. max. min. max. write cycle time t wc 100 120 150 ns /ce1 to end of write t cw1 80 100 120 ns ce2 to end of write t cw2 80 100 120 ns address valid to end of write t aw 80 100 120 ns address setup time t as 0 0 0 ns write pulse width t wp 60 85 100 ns write recovery time t wr 0 0 0 ns data valid to end of write t dw 60 60 80 ns data hold time t dh 0 0 0 ns /we to output in high impedance t whz 35 40 50 ns note output active from end of write t ow 5 5 5 ns note see the output load . remark these ac characteristics are in common regardless of package types.
data sheet m11657ejdv0ds 16 pd431000a write cycle timing chart 1 (/we controlled) t wc t cw1 t whz t dw t dh t ow indefinite data out high impe- dance high impe- dance data in indefinite data out address (input) /ce1 (input) i/o (input / output) ce2 (input) t cw2 t aw t wp t as t wr /we (input) cautions 1. during address transition, at least one of pins /ce1, ce2, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. remarks 1. write operation is done during the overlap time of a low level /ce1, /we and a high level ce2. 2. if /ce1 changes to low level at the same time or after the change of /we to low level, or if ce2 changes to high level at the same time or after the change of /we to low level, the i/o pins will remain high impedance state. 3. when /we is at low level, t he i/o pins are always high impedance. when /we is at high level, read operation is executed. ther efore /oe should be at high level to make the i/o pins high impedance.
data sheet m11657ejdv0ds 17 t wc t as t cw1 t dw t dh data in high impedance address (input) /ce1 (input) i/o (input) high impedance ce2 (input) t cw2 t aw t wp t wr /we (input) cautions 1. during address transition, at least one of pins /ce1, ce2, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. remark write operation is done during the overlap time of a low level /ce1, /we and a high level ce2.
data sheet m11657ejdv0ds 18 pd431000a write cycle timing chart 3 (ce2 controlled) t wc t as t cw2 t dw t dh data in high impedance address (input) ce2 (input) i/o (input) high impedance /ce1 (input) t cw1 t aw t wp t wr /we (input) cautions 1. during address transition, at least one of pins /ce1, ce2, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. remark write operation is done during the overlap time of a low level /ce1, /we and a high level ce2.
data sheet m11657ejdv0ds 19 c) parameter symbol test condition pd431000a-xxl pd431000a-xxll unit pd431000a-axx pd431000a-bxx min. typ. max. min. typ. max. data retention v ccdr1 /ce1 v cc ? 0.2 v, 2.0 5.5 2.0 5.5 v supply voltage ce2 v cc ? 0.2 v v ccdr2 ce2 0.2 v 2.0 5.5 2.0 5.5 data retention i ccdr1 v cc = 3.0 v, /ce1 v cc ? 0.2 v, 1 50 note1 0.5 10 note2 a supply current ce2 v cc ? 0.2 v i ccdr2 v cc = 3.0 v, ce2 0.2 v 1 50 note1 0.5 10 note2 chip deselection t cdr 0 0 ns to data retention mode operation t r 5 5 ms recovery time notes 1. 15 a (t a 40 c) 2. 3 a (t a 40 c)
data sheet m11657ejdv0ds 20 pd431000a data retention timing chart (1) /ce1 controlled v ih (min.) v ccdr (min.) v il (max.) v cc /ce1 /ce1 v cc ? 0.2 v gnd 4.5 v note t cdr data retention mode t r note a version : 3.0 v, b version : 2.7 v remark on the data retention mode by controlling /ce1, the input level of ce2 must be ce2 v cc ? 0.2 v or ce2 0.2 v. the other pins (address, i/o, /we, /oe) can be in high impedance state. (2) ce2 controlled v ih (min.) v ccdr (min.) v il (max.) v cc ce2 ce2 0.2 v gnd 4.5 v note t cdr data retention mode t r note a version : 3.0 v, b version : 2.7 v remark on the data retention mode by cont rolling ce2, the other pins (/ce1, address, i/o, /we, /oe) can be in high impedance state.
data sheet m11657ejdv0ds 21 32-pin plastic dip (15.24mm(600)) notes 1. each lead centerline is located within 0.25 mm of its true position (t.p.) at maximum material condition. item millimeters a 40.64 max. b 1.27 max. c 2.54 (t.p.) d 0.50 0.10 f 1.1 min. g 3.2 0.3 j 5.08 max. k 15.24 (t.p.) m 0.25 n 0.25 h 0.51 min. i 4.31 max. l 13.2 + 0.10 ? 0.05 2. item "k" to center of leads when formed parallel. p32c-100-600a-2 r 0 - 15 p 0.9 min. 32 17 116 n b i m r m c d f h g a j k l p
data sheet m11657ejdv0ds 22 pd431000a 32 17 116 s 32-pin plastic sop (13.34 mm (525)) note each lead centerline is located within 0.12 mm of its true position (t.p.) at maximum material condition. item millimeters c 0.78 max. b 20.61 max. a 1.27 (t.p.) e 0.15 0.05 f 2.95 max. g 2.7 h 14.1 0.3 i 11.3 j 1.4 0.2 d 0.40 + 0.10 ? 0.05 m 0.12 n 0.10 l 0.8 0.2 k 0.20 + 0.10 ? 0.05 p3 + 7 ? 3 p32gw-50-525a-1 k l g p dm b j detail of lead end s n a h i m f e c
data sheet m11657ejdv0ds 23 notes 32-pin plastic tsop( i ) (8x20) item millimeters a b c e i 8.0 0.1 0.5 (t.p.) 0.1 0.05 0.45 max. k 1.2 max. 18.4 0.1 0.145 0.05 f 0.10 m d 0.22 0.05 1. each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. 2. "a" excludes mold flash. (includes mold flash : 8.3 mm max.) r l 0.97 0.08 g l 0.5 0.10 n p 20.0 0.2 q3 + 5 ? 3 0.25 r s32gz-50-kjh1-2 s 0.60 0.15 j 0.8 0.2 g f e s q detail of lead end 1 16 32 17 s n s c d m m b a p k i j
data sheet m11657ejdv0ds 24 pd431000a notes 32-pin plastic tsop( i ) (8x20) item millimeters a b c e i 8.0 0.1 0.5 (t.p.) 0.1 0.05 0.45 max. k 1.2 max. 18.4 0.1 0.145 0.05 f 0.10 m d 0.22 0.05 1. each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. 2. "a" excludes mold flash. (includes mold flash : 8.3 mm max.) c r d m m g 0.97 0.08 g l 0.5 0.10 n p 20.0 0.2 q3 + 5 ? 3 0.25 r s32gz-50-kkh1-2 s 0.60 0.15 j 0.8 0.2 b f e q s l detail of lead end 1 16 32 17 s a s n k i p j
data sheet m11657ejdv0ds 25 32-pin plastic tsop( i ) (8x13.4) notes 1. each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. item millimeters p32gu-50-9jh-2 b 0.45 max. c 0.5 (t.p.) detail of lead end a 8.0 0.1 h 12.4 0.2 b t d 0.22 0.05 g 1.0 0.05 i 11.8 0.1 j 0.8 0.2 k l 0.5 m 0.08 n 0.08 q 0.1 0.05 p 13.4 0.2 s 1.2 max. r3 t 0.25 u 0.6 0.15 + 5 ? 3 2. "a" excludes mold flash. (includes mold flash : 8.3 mm max.) m u l r q s dm c g j 0.145 + 0.025 ? 0.015 1 16 32 17 s s n k h p i a
data sheet m11657ejdv0ds 26 pd431000a + 0.025 ? 0.015 32-pin plastic tsop( i ) (8x13.4) notes 1. each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. item millimeters p32gu-50-9kh-2 b 0.45 max. c 0.5 (t.p.) detail of lead end a 8.0 0.1 h 12.4 0.2 t d 0.22 0.05 g 1.0 0.05 i 11.8 0.1 j 0.8 0.2 k l 0.5 m 0.08 n 0.08 q 0.1 0.05 p 13.4 0.2 s 1.2 max. r3 t 0.25 u 0.6 0.15 + 5 ? 3 2. "a" excludes mold flash. (includes mold flash : 8.3 mm max.) u l r q s 0.145 1 16 32 17 s n s b m d m c g a k h p ij
data sheet m11657ejdv0ds 27 please consult with our sales offi ces for soldering conditions of the pd431000a. types of surface mount device pd431000agw-xxl : 32-pin plastic sop (13.34 mm (525)) pd431000agw-xxll : 32-pin plastic sop (13.34 mm (525)) pd431000agw-axx : 32-pin plastic sop (13.34 mm (525)) pd431000agw-bxx : 32-pin plastic sop (13.34 mm (525)) pd431000agz-xxll-kjh : 32-pin plastic tsop(i) (8x20) (normal bent) pd431000agz-xxll-kkh : 32-pin plastic tsop(i) (8x20) (reverse bent) pd431000agz-bxx-kjh : 32-pin plastic tsop(i) (8x20) (normal bent) pd431000agu-bxx-9jh : 32-pin plastic tsop(i) (8x13.4) (normal bent) pd431000agu-bxx-9kh : 32-pin plastic tsop(i) (8x13.4) (reverse bent) pd431000agw-xxl-a : 32-pin plastic sop (13.34 mm (525)) pd431000agw-xxll-a : 32-pin plastic sop (13.34 mm (525)) pd431000agw-axx-a : 32-pin plastic sop (13.34 mm (525)) pd431000agw-bxx-a : 32-pin plastic sop (13.34 mm (525)) pd431000agz-xxll-kjh-a : 32-pin plastic tsop(i) (8x20) (normal bent) pd431000agz-xxll-kkh-a : 32-pin plastic tsop(i) (8x20) (reverse bent) pd431000agz-bxx-kjh-a : 32-pin plastic tsop(i) (8x20) (normal bent) pd431000agu-bxx-9jh-a : 32-pin plastic tsop(i) (8x13.4) (normal bent) pd431000agu-bxx-9kh-a : 32-pin plastic tsop(i) (8x13.4) (reverse bent) types of through hole mount device pd431000acz-xxl : 32-pin plastic dip (15.24 mm (600)) pd431000acz-xxll : 32-pin plastic dip (15.24 mm (600)) soldering process so ldering conditions wave soldering (only to leads) solder temperature: 260 c or below, flow time: 10 seconds or below partial heating method pin temperature : 300 c or below, time: 3 seconds or below (per one lead) caution do not jet molten solder on the surface of package.
data sheet m11657ejdv0ds 28 pd431000a revision history edition/ page type of description date this previous revision edition edition 13th edition/ through through modification ordering information revised. nov. 2008
data sheet m11657ejdv0ds 29
data sheet m11657ejdv0ds 30 pd431000a [memo]
data sheet m11657ejdv0ds 31 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
pd431000a the information in this document is current as of november, 2008. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers mu st incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of an nec electronics pr oduct depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if cu stomers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":

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